1. Field of the Invention
The present invention relates to a semiconductor memory device and a driving method for the device. For example, the invention relates to the semiconductor memory device which stores data according to a number of majority carriers stored in a floating body, and the driving method for the device.
2. Related Art
In recent years, semiconductor memory devices which are expected as memories instead of DRAM include FBC (Floating Body Cell) memories. An FBC memory has an N-type MOS transistor having a floating body (hereinafter, also as a body region) on an SOI (Silicon On Insulator) substrate.
The FBC memory stores data “1” or data “0” according to a number of holes accumulated in the body region.
In one example, a state that the number of holes in the body region is large is data “1”, and a state that the number of holes is small is data “0”. In this case, a threshold voltage of a memory cell for storing data “1” (hereinafter, also as “1” cell) becomes lower than a threshold voltage of a memory cell for storing data “0” (hereinafter, also as “0” cell). When data is read from the memory cell, an electric potential of a bit line connected to the “1” cell becomes lower than an electric potential of a bit line connected to the “0” cell. Therefore, when the same data as the read data is written back to the memory cell, a sense amplifier should apply an electric potential corresponding to data obtaining logically inverting the read data to the memory cell. For this reason, in a conventional FBC memory, the sense amplifier necessarily has a latch circuit for holding read data at a sense node and a transfer gate for connecting a bit line different from the bit line connected at the time of reading to the sense node.
However, when data is written back to the memory cell, a writing power supply voltage is transmitted to the bit line via the transfer gate and the transistor composing the latch circuit. The transistor and the transfer gate drop the power supply voltage. As a result, an electric current which is sufficient for writing data cannot be applied to the memory cell, or the data writing time becomes long. This causes a defect of data writing. Conventionally, in order to repress the voltage drop, the transistor and the transfer gate in the latch circuit should be designed so as to have large sizes (W (channel width)/L (channel length)).
The latch circuit should drive also a DQ line which connects a DQ buffer for temporarily storing reading/writing data to the sense amplifier at the time of data reading/writing. For this reason, the size (W/L) of the transistor in the latch circuit should be sufficiently large. If this size is small, the reading/writing time is prolonged. When the transistor and the transfer gate in the latch circuit have a large size, a circuit size of the sense amplifier becomes large. Since the sense amplifier is provided to each bit line pair, its large circuit size causes an increase in the entire FBC memory device.